Calibrated SAR ADC having a reduced size
US9319059B1 · kind B1 · utility
13Cited by
4References
18Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Jun 6, 2015 |
| Grant date | Apr 19, 2016 |
| Priority date | — |
| Expiry date | Jun 6, 2035 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03M1/468
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
The silicon real estate required for the semiconductor fabrication of a calibrated capacitor-based successive approximation register (SAR) analog-to-digital converter (ADC) (100) is substantially reduced by using a number of shared capacitors (SC1-SCs−1) which are used as calibration capacitors when operating in a calibration mode and as bit capacitors when operating in a normal mode.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.