Gate drive under-voltage detection
US9322852B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jul 15, 2014 |
| Grant date | Apr 26, 2016 |
| Priority date | — |
| Expiry date | Sep 8, 2034 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH02M7/53871
- WIPO fieldElectrical machinery, apparatus, energy
- WIPO sectorElectrical engineering
Abstract
Gate drive faults are detected for an inverter which comprises a phase switch having an insulated gate, such as an IGBT. A complementary transistor pair is adapted to receive a supply voltage and a pulse-width modulated (PWM) signal to alternately charge and discharge the insulated gate. A comparator compares the voltage at the insulated gate with a reference voltage representing a gate drive fault to generate a first logic signal. A latch samples the first logic signal when the PWM signal has a value corresponding to charging the insulated gate. A logic circuit inhibits charging of the insulated gate when the latched logic signal indicates the gate drive fault. An insulated gate voltage less than the reference voltage is indicative of an under-voltage fault as well as other device failures of the IGBT or the complementary transistors.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.