Array substrate and liquid crystal display panel comprising dual gate lines having TFT and pixel connection between the gate lines
US9323122B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | May 16, 2013 |
| Grant date | Apr 26, 2016 |
| Priority date | — |
| Expiry date | Nov 25, 2033 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG02F1/13624
- WIPO fieldOptics
- WIPO sectorInstruments
Abstract
Embodiments provide an array substrate and a liquid crystal display panel. The array substrate comprises: a substrate, data lines and gate lines which are provided on the substrate and intersect with each other, and sub-pixel units which are defined by surrounding of the data lines and the gate lines and are arranged in an array form. Two gate lines for respectively driving the sub-pixel units in two adjacent rows are located between the sub-pixel units in the two adjacent rows; each sub-pixel unit comprises a thin film transistor (TFT) and a pixel electrode, and a connection area of the TFT and the pixel electrode is located between the two gate lines adjacent to the sub-pixel unit and has no overlapping area with a projection of the two gate lines in a perpendicular direction of the array substrate.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.