Identifying and prioritizing critical instructions within processor circuitry
US9323678B2 · kind B2 · utility
2Cited by
7References
21Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Dec 30, 2011 |
| Grant date | Apr 26, 2016 |
| Priority date | — |
| Expiry date | Aug 27, 2032 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F13/14
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
In one embodiment, the present invention includes a method for identifying a memory request corresponding to a load instruction as a critical transaction if an instruction pointer of the load instruction is present in a critical instruction table associated with a processor core, sending the memory request to a system agent of the processor with a critical indicator to identify the memory request as a critical transaction, and prioritizing the memory request ahead of other pending transactions responsive to the critical indicator. Other embodiments are described and claimed.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.