Clamping circuit for multiple-port memory cell
US9324415B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | Feb 12, 2014 |
| Grant date | Apr 26, 2016 |
| Priority date | — |
| Expiry date | Mar 24, 2034 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C11/412
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A circuit includes a memory cell, a first data line, a second data line, and a clamping unit. The memory cell includes a data node, a first pass gate, and a second pass gate. The first pass gate is between the first data line and the data node. The second pass gate is between the second data line and the data node. The clamping unit is electrically coupled to the first data line and configured to pull a voltage level of the first data line toward a clamped voltage level when the clamping unit is enabled, and to function as an open circuit to the first data line when the clamping unit is disabled. The clamping unit is disabled when a first control signal indicates that a voltage level of the second data line is pulled toward a reference voltage level.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.