Diode circuit layout topology with reduced lateral parasitic bipolar action

US9324701B2 · kind B2 · utility

Assignee

• Silicon Laboratories Inc. · US

Inventors

• Jeremy C. Smith · Austin, US
• Anirudh Oberoi · Rochester, US
• William E. Moore · Macedon, US
• Michael G. Khazhinsky · Austin, US

Key dates

• Filing date: Feb 11, 2014
• Grant date: Apr 26, 2016
• Expiry date: Nov 7, 2034

Classification

• Technology area (CPC H): Electricity
• CPC primary: H10D89/611

Abstract

Diode circuit layout topologies and methods are disclosed that exhibit reduced lateral parasitic bipolar characteristics at lateral parasitic bipolar circuit emitter edges during ESD or other voltage events as compared to conventional circuit layout topologies. The disclosed diode circuit layout topologies may be implemented to recess parasitic emitter ends relative to surrounding well ties, for example, to reduce or substantially eliminate parasitic bipolar action at lateral emitter edges of the circuitry during ESD events so as to provide higher current threshold for device failure, allowing for smaller device area and/or improved ESD robustness for a given circuit device.