Power semiconductor device
US9324708B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Dec 17, 2012 |
| Grant date | Apr 26, 2016 |
| Priority date | — |
| Expiry date | Aug 3, 2033 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D62/393
Abstract
An exemplary power semiconductor device with a wafer having an emitter electrode on an emitter side and a collector electrode on a collector side, an (n-) doped drift layer, an n-doped first region, a p-doped base layer, an n-doped source region, and a gate electrode, all of which being formed between the emitter and collector electrodes. The emitter electrode contacts the base layer and the source region within a contact area. An active semiconductor cell is formed within the wafer, and includes layers that lie in orthogonal projection with respect to the emitter side of the contact area of the emitter electrode. The device also includes a p-doped well, which is arranged in the same plane as the base layer, but outside the active cell. The well is electrically connected to the emitter electrode at least one of directly or via the base layer.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.