Vertical memory devices and methods of manufacturing the same
US9324730B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jan 21, 2015 |
| Grant date | Apr 26, 2016 |
| Priority date | — |
| Expiry date | Jan 21, 2035 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D89/10
Abstract
A vertical memory device including a substrate including first regions and a second region; a plurality of channels in the first regions, the plurality of channels extending in a first direction substantially perpendicular to a top surface of the substrate; a charge storage structure on a sidewall of each channel in a second direction substantially parallel to the top surface of the substrate; a plurality of gate electrodes in the first regions, the plurality of gate electrodes arranged on a sidewall of the charge storage structure and spaced apart from each other in the first direction; and a plurality of supporters in the second region, the plurality of supporters spaced apart from each other in a third direction substantially perpendicular to the first direction and the second direction, the plurality of supporters contacting a sidewall of at least one gate electrode.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.