Programmable filter
US9325302B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Dec 3, 2014 |
| Grant date | Apr 26, 2016 |
| Priority date | — |
| Expiry date | Dec 3, 2034 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03H2015/007
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
In several embodiments of the invention, a programmable architecture for FIR filters includes a tapped delay chain and a number of different slices. Each slice has a multiplexer that receives all of the tapped input-signal samples and a programmable current driver. Each slice can be independently programmed to correspond to any one of the taps in the delay chain, such that zero, one, or more slices can be associated with any of the delay-chain taps. Moreover, the current driver in each slice can be independently programmed to contribute any available driver strength level for the selected tap, where the combination of one or more drive strengths associated with a given tap corresponds to the effective tap coefficient for that tap. In this way, the architecture can be programmed to provide a variety of different filters having not just transfer functions with different coefficient values, but also transfer functions having different numbers of pre-cursor and/or post-cursor taps.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.