Active biasing in metal oxide semiconductor (MOS) differential pairs
US9325305B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Mar 10, 2014 |
| Grant date | Apr 26, 2016 |
| Priority date | — |
| Expiry date | Jun 28, 2034 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K19/018514
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
Apparatus and methods advantageously maintain transistors of open-drain differential pairs biased in the saturation region when “active,” rather in than the triode or linear region. The biasing techniques are effective over a broad range of process, voltage, and temperature (PVT) variations. By controlling a high voltage level used to drive the gate of a transistor of the differential pair, the biasing of the transistor in the saturation region is maintained. In one embodiment, the low voltage level used to cut off the transistor of the differential pair is also controlled. These techniques advantageously permit differential drivers to exhibit relatively large output swings, relatively high edge rates, relatively high return loss, and relatively good efficiency.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.