Referenceless clock and data recovery circuit
US9325490B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Mar 20, 2014 |
| Grant date | Apr 26, 2016 |
| Priority date | — |
| Expiry date | Apr 5, 2034 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04L7/0332
- WIPO fieldDigital communication
- WIPO sectorElectrical engineering
Abstract
A circuit and method for referenceless CDR with improved efficiency and jitter tolerance by using an additional loop for frequency detection. Such an improved circuit includes a frequency detector for identifying whether an initial recovered clock signal is faster or slower than the actual bit rate of the received data stream. The frequency detector provides a jitter tolerance of +/−0.5 UI and uses significantly fewer components that other conventional frequency detectors. Having fewer components, significantly less power is also consumed. In an embodiment, the FD uses only four flip-flops, two AND gates, and one delay circuit. Having fewer components also uses less die space in integrated circuits. Having high jitter tolerance and fewer components is an improvement over conventional referenceless CDR circuits.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.