Modular frequency divider with switch configuration to reduce parasitic capacitance
US9325541B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | May 16, 2014 |
| Grant date | Apr 26, 2016 |
| Priority date | — |
| Expiry date | Jun 4, 2034 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04W52/367
- WIPO fieldDigital communication
- WIPO sectorElectrical engineering
Abstract
A system comprising a first frequency divider to divide an input frequency of an input signal to generate a first signal having a first frequency and a first phase. Each of a plurality of second frequency dividers divides the input frequency of the input signal to generate a second signal having the first frequency and a second phase. A first switch includes a first end connected to a first node of the first frequency divider, and a second end connected to a second node of a first one of the plurality of second frequency dividers. A plurality of second switches include first ends connected to the second end of the first switch, and second ends respectively connected to the second nodes of the plurality of second frequency dividers other than the first one of the plurality of second frequency dividers.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.