Low power management of multiple sensor chip architecture
US9329701B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jun 28, 2013 |
| Grant date | May 3, 2016 |
| Priority date | — |
| Expiry date | Jan 6, 2034 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY02D30/70
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A method, device, system, or article of manufacture is provided for low-power management of multiple sensor chip architecture. In one embodiment, a method comprises, at a computing device that includes a first processor, a second processor and a third processor, receiving, at the first processor, first sensor data from a first sensor; determining, at the first processor, a motion state of the computing device using the first sensor data; in response to determining that the motion state corresponds to a predetermined motion state, activating the second processor; receiving, at the second processor, second sensor data from a second sensor; determining, by the second processor, that the motion state corresponds to the predetermined motion state using the second sensor data; and, in response to determining that the motion state corresponds to the predetermined motion state using the second sensor data, sending the motion state to the third processor.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.