Intelligent parametric scratchap memory architecture
US9329834B2 · kind B2 · utility
1Cited by
13References
20Claims
0Family size
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Key dates
| Filing date | Dec 28, 2012 |
| Grant date | May 3, 2016 |
| Priority date | — |
| Expiry date | Jun 1, 2033 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F15/8007
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
An electronic apparatus may be provided that includes a processor to perform operations, and a memory subsystem including a plurality of parallel memory banks to store a two-dimensional (2D) array of data using a shifted scheme. Each memory bank may include at least two elements per bank word.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.