Method and apparatus for the definition and generation of configurable, high performance low-power embedded microprocessor cores
US9329872B2 · kind B2 · utility
3Cited by
5References
15Claims
0Family size
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Key dates
| Filing date | Apr 29, 2013 |
| Grant date | May 3, 2016 |
| Priority date | — |
| Expiry date | Feb 23, 2034 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F15/7867
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A system and method for configuring a microprocessor core may allow a microprocessor core to be configurable. Configuration may be dynamic or automatic using an application program. Microprocessor memory, decoding units, arithmetic logic units, register banks, storage, register bypass units, and a user interface may be configured. The configuration may also be used to optimize an instruction set to run on the microprocessor core.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.