Overlapping data integrity for semiconductor devices
US9329926B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Sep 13, 2013 |
| Grant date | May 3, 2016 |
| Priority date | — |
| Expiry date | Jan 14, 2034 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F11/10
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A data integrity (DI) protection circuit and method provide overlapping DI protection without increasing memory requirements. Write data parity is checked after write data error correcting code (ECC) check bits are generated, which is stored with the write data in memory without storing the write data parity. A corrupt location cache stores the write address and a write response error is generated when a write data parity error or write address parity error is detected. Read data and read data ECC check bits retrieved from the memory are checked and single bit errors are corrected, while double-bit errors result in a read error response. Read data parity is generated, and the corrected read data and corrected read data ECC check bits are then checked for bit errors. The corrupt location cache is searched for the read address, and a cache hit results in a read error response.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.