Managing translations across multiple contexts using a TLB with entries directed to multiple privilege levels and to multiple types of address spaces
US9330023B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jun 5, 2014 |
| Grant date | May 3, 2016 |
| Priority date | — |
| Expiry date | Jun 7, 2034 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2212/684
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
For a current context in control of a processor requesting access to a particular address, a translation lookaside buffer (TLB) controller specifies a virtual address with a logical partition identifier value indicating a privilege setting of the current context, a process identifier value indicating whether the address is within shared address space, and an effective address comprising at least a portion of the particular address. In response to the virtual address not matching at least one entry within a TLB comprising at least one entry stored for at least one previous translation of at least one previous address, the TLB controller translates the virtual address into a real page number using at least one page table and adding a new entry to the TLB with the virtual address and the real page number, wherein each at least one entry within the TLB identifies a separate privilege setting from among a plurality of privilege settings and a separate indicator of whether the address is within the shared address space.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.