Maintenance circuit for display panel
US9330625B2 · kind B2 · utility
Assignees
Inventors
Key dates
| Filing date | May 10, 2013 |
| Grant date | May 3, 2016 |
| Priority date | — |
| Expiry date | Jun 7, 2033 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG09G2330/08
- WIPO fieldAudio-visual technology
- WIPO sectorElectrical engineering
Abstract
A maintenance circuit for a display panel, the display panel being divided by a plurality of source driver integrated circuits into a plurality of partitions(X1-X8) corresponding thereto, wherein each of source driver integrated circuits controls one partition, each four of adjacent partitions form a group of partitions, each of the maintenance circuit units comprises: a first maintenance line(RP1, RP3) and a second maintenance line(RP2, RP4) each provided with a half-turn shape surrounding around a group of partitions corresponding thereto; a first operational amplifier(OP1, OP3) and a second operational amplifier(OP2, OP4), the inverting input terminal of each of which is connected to an output terminal thereof and is connected to a corresponding maintenance line; and a plurality of resistors(R1-R8, L1-L8) selectively connected in accordance with two partitions of the group of the partitions to be maintained, so as to respectively import the two partitions to non-inverting input terminals of the two operational amplifiers via signals outputted from a corresponding source driver integrated circuits, and to feed the signals outputted from the two operational amplifiers back to the …
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.