Multiple conductive layer TFT
US9331132B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Apr 5, 2006 |
| Grant date | May 3, 2016 |
| Priority date | — |
| Expiry date | May 13, 2029 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10K59/1201
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A multiple layer pixel architecture for an active matrix display is provided in which a common bus line is formed on a metal level which is separate from that on which the gate electrodes of the thin-film transistors (TFTS) are formed. A multilayer electronic structure adapted to solution deposition, the structure includes a TFT for driving a pixel of an active matrix optoelectronic device and a capacitor for storing charge to maintain an electrical state of said active matrix pixel, wherein the structure includes a substrate bearing at least four conducting layers separeted by at least three dielectric layers, first and second ones of said conducting layers defining drain/source electrodes and a gate electrode of said transistor respectively, and third and fourth ones of said conducting layers defining respective first and second plates of said capacitor, and wherein said capacitor and said transistor are laterally positioned such that they overlap in a vertical direction.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.