Silicon nanowire formation in replacement metal gate process
US9331146B2 · kind B2 · utility
12Cited by
8References
12Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Jun 11, 2014 |
| Grant date | May 3, 2016 |
| Priority date | — |
| Expiry date | Jun 11, 2034 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D64/691
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
Techniques for a semiconductor device are provided. Techniques are directed to forming a semiconductor device by: forming a fin structure in a substrate, forming a protective layer over an upper portion of the fin structure, the protective layer having an etch selectivity with respect to a material of the fin structure, and performing an undercut etch so as to remove a lower portion of the fin structure below the protective layer, thereby defining a nanowire structure from the fin structure.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.