Methods and systems for using conformal filling layers to improve device surface uniformity
US9331147B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | May 24, 2015 |
| Grant date | May 3, 2016 |
| Priority date | — |
| Expiry date | May 24, 2035 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D62/832
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
The invention discloses a treatment process for a semiconductor, comprising providing a substrate; defining a trench opening region of the substrate; performing plasma etching to form a trench region at the trench opening region; subjecting the substrate to a first epitaxial process with a first plurality of gaseous species to form a protective layer overlaying at least the first sidewall and the bottom of the trench region; and subjecting the substrate and the protective layer to a second epitaxial process with a second plurality of gaseous species to form a filling material overlaying the protective layer and being positioned at least partially within the trench region. The invention further provides a semiconductor processing technique used to eliminate or reduce dislocation defect on the semiconductor device and improve device performance. In the treatment process, at least one epitaxial process to form the protective layer overlaying at least the first sidewall and the bottom of the trench region corresponds to form a filling material overlaying the protective layer and being positioned at least partially within the trench region.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.