Dual squelch detectors and methods for low power states
US9331654B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Mar 22, 2013 |
| Grant date | May 3, 2016 |
| Priority date | — |
| Expiry date | Jun 15, 2033 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY02D10/00
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
An apparatus includes a first squelch circuit and a second squelch circuit. The first squelch circuit is configured to detect possible squelch signals in a communication signal. The second squelch circuit is configured to selectively detect the possible squelch signals in the same communication signal. The second squelch circuit is further configured to operate in a low-power state responsive to the first squelch circuit detecting none of the possible squelch signals in the communication signal. The second squelch circuit is further configured to operate in a high-power state responsive to the first squelch circuit detecting one of the possible squelch signals in the communication signal.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.