Shared memory controller and method of using same
US9335934B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Apr 29, 2014 |
| Grant date | May 10, 2016 |
| Priority date | — |
| Expiry date | Dec 10, 2034 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F13/1605
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Disclosed herein are a shared memory controller and a method of controlling a shared memory. An embodiment method of controlling a shared memory includes concurrently scanning-in a plurality of read/write commands for respective transactions. Each of the plurality of read/write commands includes respective addresses and respective priorities. Additionally, each of the respective transactions is divisible into at least one beat and at least one of the respective transactions is divisible into multiple beats. The method also includes dividing the plurality of read/write commands into respective beat-level read/write commands and concurrently arbitrating the respective beat-level read/write commands according to the respective addresses and the respective priorities. Concurrently arbitrating yields respective sequences of beat-level read/write commands corresponding to the respective addresses. The method further includes concurrently dispatching the respective sequences of beat-level read/write commands to the shared memory, thereby accessing the shared memory.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.