System and method for cycle slip correction
US9336079B2 · kind B2 · utility
2Cited by
2References
17Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Dec 11, 2013 |
| Grant date | May 10, 2016 |
| Priority date | — |
| Expiry date | Mar 8, 2034 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04L1/004
- WIPO fieldTelecommunications
- WIPO sectorElectrical engineering
Abstract
A system and method including a parity bit encoder for encoding bits of data to be transmitted with first and second parity check bits to produce successive block of bits. Each of the blocks of bits are Gray mapped to a plurality of associated QAM symbols that are modulated onto an optical wavelength and transmitted to a receiver. A de-mapper corrects for 90 degree and 180 degree cycle slip using parity indicated by the first and second parity bits.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.