Parallel status polling of multiple memory devices
US9336112B2 · kind B2 · utility
2Cited by
8References
18Claims
0Family size
Assignee
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Key dates
| Filing date | Aug 23, 2012 |
| Grant date | May 10, 2016 |
| Priority date | — |
| Expiry date | Jun 22, 2033 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F13/1678
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
An apparatus includes an interface and a processor. The interface is configured to communicate with multiple memory devices over a bus that includes a plurality of parallel data lines. The processor is configured to request the memory devices to provide respective status reports, and to receive the status reports from the memory devices such that, in a given clock cycle of the bus, the multiple status reports from the respective memory devices are received in parallel over respective different subsets of the data lines of the bus.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.