Systems and methods for hardware-assisted type checking
US9336125B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Aug 24, 2012 |
| Grant date | May 10, 2016 |
| Priority date | — |
| Expiry date | Jul 4, 2034 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F11/0772
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Devices and methods of providing hardware support for dynamic type checking are provided. In some embodiments, a processor includes a type check register and support for one or more checked load instructions. In some embodiments, normal load instructions are replaced by a compiler with the checked load instructions. In some embodiments, to perform a checked load, an error handler instruction location is stored in the type check register, and a type tag operand is compared to a type tag stored in the loaded memory location. If the comparison succeeds, execution may proceed normally. If the comparison fails, execution may be transferred to the error handler instruction. In some embodiments, type prediction is performed to determine whether a checked load instruction is likely to fail.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.