Enhanced I/O performance in a multi-processor system via interrupt affinity schemes
US9336168B2 · kind B2 · utility
5Cited by
1References
16Claims
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Key dates
| Filing date | Sep 25, 2015 |
| Grant date | May 10, 2016 |
| Priority date | — |
| Expiry date | Sep 25, 2035 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F13/24
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Disclosed herein is a method for improving Input/Output (I/O) performance in a host system having multiple CPUs. Under this method, various interrupt affinity schemes are provided, which associate multiple processors, interrupts, and I/O channels for sending the interrupts, thereby allowing the interrupts to be almost evenly loaded among the multiple I/O channels and processors. Also, data locality (“warm cache”) can be achieved through the interrupt affinity schemes that associate each interrupt to its source processor, namely, the processor originating the I/O request that results in the interrupt.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.