Integral fabrication of asymmetric CMOS transistors for autonomous wireless state radios and sensor/actuator nodes
US9336346B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | Jan 30, 2014 |
| Grant date | May 10, 2016 |
| Priority date | — |
| Expiry date | Nov 17, 2034 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D89/10
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A method of arranging asymmetrically doped CMOS transistors in a semiconductor wafer that forms base cells within a plurality of logic standard cells in a CMOS process technology that includes conventional symmetric CMOS transistors having different threshold voltages. The asymmetrically doped CMOS transistors have a gate length exceeding 1.5 times the minimum gate length of the symmetric CMOS transistors. Regions defined by electrical junctions directly adjacent to the gate of the asymmetric transistors are formed by an implant mask exposing an area of the wafer on the source side of the transistor to receive the junction implant of the symmetric CMOS transistors with a higher threshold voltage while shielding the drain area, and a further implant mask exposing an area of the wafer on the drain side of the transistor to receive the junction implant of the symmetric CMOS transistors with a lower threshold voltage while shielding the source area.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.