Apparatus for time domain offset cancellation to improve sensing margin resistive memories
US9336873B2 · kind B2 · utility
2Cited by
3References
19Claims
0Family size
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Key dates
| Filing date | Dec 2, 2013 |
| Grant date | May 10, 2016 |
| Priority date | — |
| Expiry date | Mar 22, 2034 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C13/004
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Described are apparatuses for time domain offset cancellation. One example of the apparatus includes: a variable resistance memory cell; a reference resistive memory cell; a detector to generate an output indicating timing relationship between a pulse arriving from the variable resistance memory cell and a pulse arriving from the reference resistive memory cell; and a logic unit to receive the output from the detector and to generate a control signal to the adjust timing relationship as indicated by the detector.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.