Reading and writing to NAND flash memories using charge constrained codes
US9336885B1 · kind B1 · utility
0Cited by
1References
20Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | May 23, 2013 |
| Grant date | May 10, 2016 |
| Priority date | — |
| Expiry date | Jan 25, 2034 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C2029/0411
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A charge constrained bit sequence is processed to obtain a lower bound on a number of bit errors associated with the charge constrained bit sequence. The lower bound is compared against an error correction capability threshold associated with an error correction decoder. In the event the lower bound is greater than or equal to the error correction decoder threshold, an error correction decoding failure is predicted.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.