Nonvolatile memory device including memory cell array with upper and lower word line groups
US9336887B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Oct 13, 2014 |
| Grant date | May 10, 2016 |
| Priority date | — |
| Expiry date | Oct 13, 2034 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C2211/5641
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A nonvolatile memory device includes a memory cell array having multiple memory blocks. Each memory block includes memory cells arranged at intersections of multiple word lines and multiple bit lines. At least one word line of the multiple word lines is included in an upper word line group and at least one other word line of the multiple word lines is included in a lower word line group. The number of data bits stored in memory cells connected to the at least one word line included in the upper word line group is different from the number of data bits stored in memory cells connected to the at least one other word line included in the lower word line group.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.