Apparatus and methods for annealing wafers
US9337059B2 · kind B2 · utility
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1References
19Claims
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Key dates
| Filing date | Aug 23, 2011 |
| Grant date | May 10, 2016 |
| Priority date | — |
| Expiry date | Apr 12, 2034 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L21/324
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A method includes performing an anneal on a wafer. The wafer includes a wafer-edge region, and an inner region encircled by the wafer-edge region. During the anneal, a first power applied on a portion of the wafer-edge region is at least lower than a second power for annealing the inner region.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.