Stack chip package image sensor
US9337228B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Aug 26, 2014 |
| Grant date | May 10, 2016 |
| Priority date | — |
| Expiry date | Aug 26, 2034 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10F39/809
Abstract
An image sensor cell is divided into two chips, and a capacitor for noise reduction is formed in a bottom wafer in correspondence with a unit pixel of a top wafer in a stack chip package image sensor having a coupling structure of the two chips, so that noise characteristics of the image sensor are improved. A stack chip package image sensor includes: a first semiconductor chip that includes a photodiode, a transmission transistor, and a first conductive pad and outputs image charge, which is output from the photodiode, through the first conductive pad; and a second semiconductor chip that includes a drive transistor, a selection transistor, a reset transistor, and a second conductive pad and supplies a corresponding pixel with an output voltage corresponding to the image charge received from the first semiconductor chip through the second conductive pad. The second semiconductor chip includes a capacitor for noise reduction.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.