III-Nitride insulating-gate transistors with passivation
US9337332B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | May 29, 2014 |
| Grant date | May 10, 2016 |
| Priority date | — |
| Expiry date | May 29, 2034 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D64/685
Abstract
A field-effect transistor (FET) includes a plurality of semiconductor layers, a source electrode and a drain electrode contacting one of the semiconductor layers, a first dielectric layer on a portion of a top semiconductor surface between the source and drain electrodes, a first trench extending through the first dielectric layer and having a bottom located on a top surface or within one of the semiconductor layers, a second dielectric layer lining the first trench and covering a portion of the first dielectric layer, a third dielectric layer over the semiconductor layers, the first dielectric layer, and the second dielectric layer, a second trench extending through the third dielectric layer and having a bottom located in the first trench on the second dielectric layer and extending over a portion of the second dielectric, and a gate electrode filling the second trench.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.