Controller with power saving for power converters and method for the same
US9337736B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Mar 6, 2013 |
| Grant date | May 10, 2016 |
| Priority date | — |
| Expiry date | Aug 15, 2033 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY02B70/10
- WIPO fieldElectrical machinery, apparatus, energy
- WIPO sectorElectrical engineering
Abstract
A controller with power saving for a power converter includes a delay circuit, a detection circuit, an output circuit, a counter circuit, a wake-up circuit and a PWM circuit. The delay circuit determines a delay time. The detection circuit activates the delay circuit whenever an output load of the power converter is lower than a light-load threshold. The output circuit generates a power-saving signal to cease a regulation of the power converter after the delay time ends. The regulation of the power converter is resumed once the output load increases during the regulation of the power converter is being ceased. The counter circuit coupled to the delay circuit is counted by the delay circuit to determine a sleep period. The output circuit generates the power-saving signal to cease the regulation of the power converter after the sleep period ends.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.