Power amplifier with improved low bias mode linearity
US9337787B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jun 13, 2014 |
| Grant date | May 10, 2016 |
| Priority date | — |
| Expiry date | Jun 13, 2034 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03G3/30
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
Power amplifier circuitry includes a power amplifier including an input node and an output node, biasing circuitry, a selectable impedance network, and an input capacitor. The input capacitor is coupled to the input node of the power amplifier. The biasing circuitry is coupled to the input node of the power amplifier through the selectable impedance network. The power amplifier is operable in a low power operating mode and a high power operating mode. In the low power operating mode, the biasing circuitry delivers a first biasing current to the input node of the power amplifier, and a first impedance level of the selectable impedance is selected. In the high power operating mode, the biasing circuitry delivers a second biasing current to the input node of the power amplifier, and a second impedance level of the selectable impedance is selected.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.