Differential receiver
US9337789B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Oct 8, 2013 |
| Grant date | May 10, 2016 |
| Priority date | — |
| Expiry date | Apr 4, 2034 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03F2203/45648
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A differential receiver with reduced common mode induced propagation delay variance. One implementation of a differential receiver includes a first differential amplifier, a second differential amplifier, and a first current source. The first differential amplifier includes a first transistor pair. The second differential amplifier includes a second transistor pair. The first current source is coupled to a drain node of a first transistor of the first transistor pair. The first current source is configured to generate a variable first current at the drain node as of function of a sum of a variable tail current of the first differential amplifier and a variable tail current of the second differential amplifier.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.