Solving constraint satisfaction problems using a field programmable gate array
US9337845B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jun 16, 2014 |
| Grant date | May 10, 2016 |
| Priority date | — |
| Expiry date | Sep 2, 2034 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K19/17772
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A method for configuring a Field Programmable Gate Array (FPGA) with a Constraint Satisfaction Problem (CSP) assignment having multiple constraint expressions, the method comprising: setting each of the multiple constraint expressions as a configurable logic block (CLB) in the FPGA, to yield multiple CLBs; setting an assignment vector in the FPGA, wherein the assignment vector is a number vector configured to store a candidate solution to the CSP assignment; and forming a feedback loop by connecting the assignment vector to inputs of the multiple CLBs, and connecting outputs of the multiple CLBs to the assignment vector. Further disclosed is a design structure for the FPGA, optionally residing on a storage medium as a data format used for the exchange of layout data of integrated circuits.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.