Calibration for a single ramp multi slope analog-to-digital converter
US9337856B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Sep 28, 2015 |
| Grant date | May 10, 2016 |
| Priority date | — |
| Expiry date | Sep 28, 2035 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03M1/52
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
Methods and Systems for calibrating a Single Ramp Multiple Slope Analog to Digital Converter (SRMS ADC), the ADC including a counter and a plurality N of charge and discharge elements of different time constant i.e. slope, wherein the relationships between slopes is defined as a function of the shallowest slope SN such that S1=K1·SN, S2=K2·SN, . . . SN-1=KN-1·SN-1 where the K values are integers, and the code count for conversion is C=K1·C1+K2·C2+ . . . KN-1·CN-1+CN where each Ci represents an observed counts per each slope for a conversion, including; sampling for a first calibration pass a voltage with the ADC, discharging the voltage on the steepest slope for a number of counter counts C11, charging and discharging on the remaining slopes up to K2 to KN-1 for a number of counts per slope, Ci1 e.g. C21 to CN-1,1, discharging the remaining voltage residue on the shallowest slope and note the count, CN,1, sampling the same voltage on the ADC for a second calibration pass, discharging the voltage on the steepest slope for a modified number of counter counts C12=C11+/−X, modifying the number of charge/discharge counts time Ci2 for the slopes K2 to KN-1 to adjust for the change expect…
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.