Patent · US Active

Error checking using serial collection of error data

US9342395B2 · kind B2 · utility

0Cited by

2References

18Claims

0Family size

Assignee

International Business Machines Corporation · US

Inventors

Tobias U. Bergmann · Eppelheim, DE
Guenter Gerwig · Simmozheim, DE
Scott Barnett Swaney · Catskill, US
Tobias Webel · Eppelheim, DE

Key dates

Filing date	Sep 30, 2014
Grant date	May 17, 2016
Priority date	—
Expiry date	Sep 30, 2034

Classification

Technology area (CPC G)Physics
CPC primaryG06F11/30
WIPO fieldComputer technology
WIPO sectorElectrical engineering

Abstract

Embodiments relate to implementing error data collection for a processor. Aspects of the embodiments include identifying a plurality of error state devices in a processor, each of the plurality of error state devices configured to hold a state indication, and organizing the plurality of error state devices as a sequence. Aspects also include collecting a plurality of state indications by serially sampling the state indication from each of the plurality of error state devices in an order corresponding to the sequence, sequentially storing the plurality of state indications as a single linear data array, and outputting the linear data array as a data structure. The data structure can include information regarding one or more error events based on one or more errors occurring in the processor.

Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.