Run-to-completion thread model for software bypass fail open for an inline intrusion protection system
US9342415B2 · kind B2 · utility
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20Claims
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Key dates
| Filing date | Jul 14, 2014 |
| Grant date | May 17, 2016 |
| Priority date | — |
| Expiry date | Dec 19, 2034 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04L63/1416
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A processing-based bypass “fail open” mode is provided for an intrusion prevention system by a primary process running on a first logical core (lcore) is used as a control plane, which invokes bypass-open run-to-completion threads in other lcores comprising a bypass data plane, and which spawns a secondary process to fully configure intrusion prevention threads on other lcores to create an Intrusion Prevention System data plane. Upon a ready signal from the secondary process, the primary process quiesces such that the secondary process IPS data plane exclusively owns and executes on the other lcores.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.