Processor with reconfigurable architecture including a token network simulating processing of processing elements
US9342478B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Oct 19, 2009 |
| Grant date | May 17, 2016 |
| Priority date | — |
| Expiry date | Oct 5, 2032 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY02D10/00
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Disclosed is configuration memory access technology in a processor with a reconfigurable architecture. The processor with the reconfigurable architecture includes an array of processing elements (PEs), a configuration memory and a token network. The configuration memory stores configuration data associated with controlling data flow of the respective PEs. The token network reads the configuration data from the configuration memory, estimates data flow of the PEs from the read configuration data, reads required configuration data from the configuration memory based on the estimated data flow, and supplies the required configuration data to corresponding PEs. By reducing configuration memory access frequency through a token network, power consumption may be reduced.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.