Goa circuit structure sharing goa pull-down circuits to reduce TFT stress of the goa pull-down circuits
US9343032B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | Oct 30, 2015 |
| Grant date | May 17, 2016 |
| Priority date | — |
| Expiry date | Oct 30, 2035 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG09G2320/043
- WIPO fieldAudio-visual technology
- WIPO sectorElectrical engineering
Abstract
A GOA circuit structure includes multiple twined GOA units cascaded with each other. Each twined GOA unit includes a (2N−1)-level GOA unit and a 2N-level GOA unit, which has a first pull-down holding circuit, a second pull-down holding circuit, a third pull-down holding circuit, and a fourth pull-down holding circuit connected with the (2N−1)-level gate signal point (Q(2N−1)) and the 2N-level gate signal point (Q(2N)). Through inputting a first clock signal, a second clock signal, a third clock signal, and a fourth clock signal, the first pull-down holding circuit, the second pull-down holding circuit, the third pull-down holding circuit, and the fourth pull-down holding circuit are made working alternately. The GOA circuit structure makes each portion work for ¼ time and take rest for ¾ time by sharing the pull-down holding circuit, which can reduce the TFT stress of the pull-down holding circuit.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.