Test then destroy technique for security-focused semiconductor integrated circuits
US9343377B1 · kind B1 · utility
0Cited by
3References
20Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Jan 8, 2015 |
| Grant date | May 17, 2016 |
| Priority date | — |
| Expiry date | Jan 8, 2035 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L22/14
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A method includes forming an integrated circuit device having device circuitry disposed in a device circuitry area on a substrate and a destroyable circuit formed in a destroyable circuitry area on the substrate; testing at least one operational aspect of the device circuitry using the destroyable circuit; and destroying the destroyable circuit subsequent to testing the at least one operational aspect of the device circuitry.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.