Semiconductor device
US9343457B2 · kind B2 · utility
0Cited by
4References
2Claims
0Family size
Assignee
Inventor
Key dates
| Filing date | Feb 14, 2014 |
| Grant date | May 17, 2016 |
| Priority date | — |
| Expiry date | Feb 14, 2034 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D30/60
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
In order to provide a semiconductor device having a high ESD tolerance, a source wiring (32a) is formed on a gate (31) and a source (32) in a region of an NMOS transistor (30). The source wiring (32a) electrically connects the gate (31), the source (32), and a ground terminal. A drain wiring (33a) is formed on a drain (33) in the region of the NMOS transistor (30) . The drain wiring (33a) electrically connects the drain (33) and a pad (20) serving as an external connection electrode. Moreover, in the region of the NMOS transistor (30), the drain wiring (33a) has the same wiring width as the source wiring (32a).
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.