Vertical memory devices and methods of manufacturing the same
US9343475B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jan 15, 2014 |
| Grant date | May 17, 2016 |
| Priority date | — |
| Expiry date | Jan 15, 2034 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D64/037
Abstract
In a method of a vertical memory device, insulation layers and sacrificial layers are alternately and repeatedly formed on a substrate. A hole is formed through the insulation layers and the sacrificial layers that expose a top surface of the substrate. Then, an interior portion of the hole may be enlarged. A semiconductor pattern is formed to partially fill the enlarged portion of the hole. A blocking layer, a charge storage layer and a tunnel insulation layer may be formed on a sidewall of the hole and the semiconductor pattern. Then, the tunnel insulation layer, the charge storage layer and the blocking layer are partially removed to expose a top surface of the semiconductor pattern. A channel is formed on the exposed top surface of the semiconductor pattern and the tunnel insulation layer. The sacrificial layers are replaced with gate electrodes.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.