Integrated circuit stack with strengthened wafer bonding
US9343499B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Apr 23, 2015 |
| Grant date | May 17, 2016 |
| Priority date | — |
| Expiry date | Apr 23, 2035 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10F39/809
Abstract
An integrated circuit system includes a first device and second device wafer. A wafer bonding region is disposed at an interface of a front side of a first dielectric layer of the first device wafer and a front side of a second dielectric layer of the second device wafer such that wafer bonding region bonds the first device wafer to the second device wafer. The wafer bonding region includes dielectric material having a higher silicon concentration than a dielectric material of the first and second dielectric layers of the first and second device wafers. A conductive path couples a first conductor of the first device wafer to a second conductor of the second device wafer. The conductive path is formed in a cavity etched through the wafer bonding region between the first conductor and the second conductor.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.