PN-structured gate demodulation pixel
US9343607B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Mar 20, 2013 |
| Grant date | May 17, 2016 |
| Priority date | — |
| Expiry date | Mar 20, 2033 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10F71/121
Abstract
A novel photo-sensitive element for electronic imaging purposes and, in this context, is particularly suited for time-of-flight 3D imaging sensor pixels. The element enables charge-domain photo-detection and processing based on a single gate architecture. Certain regions for n and p-doping implants of the gates are defined. This kind of single gate architecture enables low noise photon detection and high-speed charge transport methods at the same time. A strong benefit compared to known pixel structures is that no special processing steps are required such as overlapping gate structures or very high-ohmic poly-silicon deposition. In this sense, the element relaxes the processing methods so that this device may be integrated by the use of standard CMOS technology for example. Regarding time-of-flight pixel technology, a major challenge is the generation of lateral electric fields. The element allows the generation of fringing fields and large lateral electric fields.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.