Passive power factor correction circuit, electronic device applying the same and operation methods thereof
US9343956B2 · kind B2 · utility
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13References
11Claims
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Key dates
| Filing date | Mar 18, 2013 |
| Grant date | May 17, 2016 |
| Priority date | — |
| Expiry date | Mar 24, 2034 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY02B70/10
- WIPO fieldElectrical machinery, apparatus, energy
- WIPO sectorElectrical engineering
Abstract
A passive power factor correction circuit includes: a DC capacitor and an input capacitor, coupled to a rectifying circuit and charged by a DC voltage from the rectifying circuit; an output capacitor, coupled to a load; first diode and a second diode, coupled to the input capacitor and the output capacitor; and an inductor, coupled to the load, the input capacitor and the output capacitor. Charging into and discharging from the DC capacitor are completed within a half cycle of an input AC voltage.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.