Down-conversion circuit with interference detection
US9344039B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jan 23, 2013 |
| Grant date | May 17, 2016 |
| Priority date | — |
| Expiry date | Jan 23, 2033 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03D2200/0088
- WIPO fieldTelecommunications
- WIPO sectorElectrical engineering
Abstract
A down-conversion circuit for a receiver circuit is disclosed. It comprises a first mixer arranged to down-convert an RF signal with a first LO signal (LO1), thereby generating a first down-converted signal. It further comprises a second mixer arranged to down-convert the RF signal with a second LO signal (LO2) having the same LO frequency as the first LO signal (LO1), but a different and a second duty cycle, thereby generating a second down-converted signal. The second mixer has an enabled and a disabled mode. The down-conversion circuit also comprises a third mixer arranged to down-convert the RF signal with the second LO signal (LO2), thereby generating a third down-converted signal. A passive output combiner network is used to combine the first and the second down-converted signals such that harmonically down-converted signal content present in the first down-converted signal and harmonically down-converted signal content present in the second down-converted signal cancel in a combined output signal of the down-conversion circuit. The down-conversion circuit further comprises a detection unit adapted to detect interference based on the first and third down-converted signals and…
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.